In general, in a semiconductor test device, a test pattern signal is input into a semiconductor device (device under test: DUT) which is a test object, a response signal output from the DUT is compared with an expected pattern signal to judge agreement/disagreement, and accordingly the DUT is tested. Moreover, the semiconductor test device usually includes a timing generation circuit (TG) which generates a timing of a waveform in order to apply a test signal to the DUT at a predetermined timing.
FIG. 10 is a block diagram showing a basic configuration of a general semiconductor memory test device.
As shown in FIG. 10, the memory test device includes: a timing generation circuit (timing generator: TG) 1; a pattern generation unit 2; a waveform formatter 3; a logical comparison unit 4; and a failure analysis memory unit 5, thereby constituting a memory test device for testing a memory M.
The timing generation circuit 1 generates a reference clock in a semiconductor memory test device.
The pattern generation unit 2 generates an address signal to be applied to the memory M to be tested which is a test object, test pattern data, control signal, and expected value data to be applied to the logical comparison unit 4 in accordance with the reference clock generated by the timing generation circuit 1.
The address signal, test pattern data, and control signal output from the pattern generation unit 2 are input into the waveform formatter 3 to format waveforms, and applied to the memory M to be tested.
In the memory M to be tested, a write or read operation of a data signal is performed based on the supplied control signal, data is read out of the applied address, and the applied write data is written into the address. The data read out of the memory M to be tested is output as a response signal, and supplied to the logical comparison unit 4.
On inputting the response signal from the memory M to be tested, and the expected value data generated by the pattern generation unit 2, the logical comparison unit 4 compares both the data to detect the agreement/disagreement. Accordingly, it is judged whether or not the memory M under test is satisfactory.
Fail data is inputted into the failure analysis memory unit 5 in a case where the response signal from the memory M to be tested disagrees with the expected value data. The fail data is stored in a memory cell corresponding to the address signal output from the pattern generation unit. The fail data stored in the failure analysis memory unit 5 is separately read out and used in analyzing the failure of the memory M.
FIG. 11 is a block diagram showing details of a conventional timing generation circuit incorporated in the semiconductor test device described above.
As shown in the figure, a conventional timing generation circuit (timing edge generation unit) comprises: a timing memory (TMM) 110 in which predetermined timing data (e.g., delay data of a reference clock) is stored; a down counter 120 for outputting a pulse signal at a predetermined timing indicated by the timing data; and a counter load enable selection circuit 130 which inputs a load signal into the down counter 120.
In this conventional timing generation circuit, the timing data stored in the timing memory 110 is set in the down counter 120, and the set timing data is loaded by the load signal of the counter load enable selection circuit 130 to thereby decrement the timing data by one in synchronization with each occurance of a CLK signal in the down counter 120.
Moreover, when the counted-down timing data indicates “0”, a pulse signal (“ALL zero” signal) is output from the down counter 120. This pulse signal is input as a timing signal into the pattern generation unit or the like (not shown).
Specifically, to operate the timing generation circuit actually in the semiconductor test device, any one of column-direction addresses (Adr: 0 to Adr: n−1 shown in FIG. 11) of the TMM 110 is designated, accordingly the data of a row-direction bit width (m bits b0 to bm−1 in an example shown in FIG. 11) stored in the address is set in the a down counter 20, and timing data can be loaded by the load signal of the counter load enable selection circuit 130 to count down. Thus, in the conventional timing generation circuit, when the timing data indicating a desired timing is stored in the TMM, for example, a timing signal can be generated which is indicated by a delay time which is an arbitrary integer multiple of a CLK signal period.
It is to be noted that the timing generation circuit is usually provided with a plurality of down counters, and, for example, as shown in FIG. 12, four-phase down counters 120a to 120d are disposed. Accordingly, while counting down the timing signal disposed in one down counter, the next timing signal is loaded on another down counter so that the down-count can be performed.
As described above, in the conventional timing generation circuit provided with the TMM in which the predetermined timing data is stored, the timing data having the row-direction bit width of the memory (TMM) can be set as many as timings set for the column-direction addresses of the memory.
However, in the conventional timing generation circuit in which a delay amount (e.g., 16 μs or less with a 20-bit width, etc.) is determined by the bit width (row direction) of the TMM in this manner, in order to handle a longer delay amount, it is necessary that a memory configuration of the TMM is changed, and the row-direction bit width is added. Moreover, it has been necessary to add a bit number per phase of the next-stage down counter. Therefore, to increase the delay amount, a circuit scale of the timing edge generation unit enormously increases, and a problem has occurred that the cost of a gate array for establishing the timing generation circuit significantly increases.
Similarly, a timing set (TS) number set to the TMM is also fixed to a column-direction address number, and there is also a problem that the timing set number cannot be increased unless the memory configuration is changed.
The present invention has been proposed to solve the above-noted problems involved in the conventional art, and an object is to provide a timing generation circuit which is capable of increasing a maximum delay amount as well as increasing a timing set number without changing a configuration of a timing memory containing timing data and which realizes a several types of TGs by one type of hardware configuration and enables low-cost device measurement. Another object of the present invention is to provide a semiconductor test device incorporating this timing generation circuit.